Design and Implementation of Equiripple FIR High Pass Filter on FPGA

Kaliprasanna Swain and Manoj Kumar Sahoo
Volume 1: Issue 1, Revised on – 30 March 2020, pp 1-4


Author's Information
Kaliprasanna Swain1 
Corresponding Author
1Gandhi Institute for Technological Advancement (GITA) /ECE, Bhubaneswar, Odisha, India.
kaleep.swain@gmail.com

Manoj Kumar Sahoo2
2Gandhi Institute for Technological Advancement (GITA) /ECE, Bhubaneswar, Odisha, India.


Research Article -- Peer Reviewed
First online on – 30 Dec 2014,      Revised on – 30 March 2020

Open Access article under Creative Commons License

Cite this article –Kaliprasanna Swain and Manoj Kumar Sahoo,, ““Design and Implementation of Equiripple FIR High Pass Filter on FPGA”, International Journal of Computational and Electronics Aspects in Engineering, RAME Publishers, vol. 1, issue 1, pp. 1-4, 2014, Revised in 2020.
https://doi.org/10.26706/ijceae.1.1.20141201


Abstract:-
This paper demonstrates the design and implementation of Equiripple linearphase FIR high pass filter. The filter is modeled using Simulink in Xilinx System Generator. The filter Coefficients are generated with the help of FDA tools, the SysGen tool is used for RTL code generation. Further the model is used as a filter block to interface with ADC/DAC block in VHDL. The design has been prototyped on Spartan-3 DSP protoboard XC3S500fg320 using Integrated Synthesis Environment (ISE) 13.1 tools all in one design suit from Xilinx. Finally the filter is tested by using an audio signal as input and the output is observed in CRO & speaker both.
Index Terms:-
Equiripple Filter, FDA Tools, Simulink, Spartan-3, Xilinx System Generator (XSG), FPGA
REFERENCES
[1] B. A. Shenoi, Introduction to digital signal processing and filter design, (JOHN WILEY & SONS, INC., 2006) pp.280- 285.

[2] UweMeyer - Baese, Digital signal processing with field programmable gate arrays, 3rd ed. (Tsinghua University Press, Beijing, 2007), pp. 175 - 177.

[3] B. Mamatha1, V.V.S.V.S. Ramachandram, “Design and implementation of 120 order fir filter based on FPGA”, International Journal of Engineering Sciences & Emerging Technologies, August 2012,Volume 3, Issue 1, pp. 90-97.

[4] Harish V. Dixit , Dr. VikasGupta,”IIR filters using Xilinx System Generator for FPGA Implementation”, IJERA,Vol. 2, Issue 5, September- October 2012, pp.303-30.

[5] ISE 13.2, Quick Start Tutorial, Xilinx.

[6] Xilinx System Generator for DSP User Guide, r10.1.1, April 2008.

[7] Nexys3™ Board Reference Manual Revision: December 28, 2011, www.digilentinc.com


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